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IC Verification

AMS Verification

Analog and AMS verification services at hand. Top-down & bottom-up, analog-on-top or digital-on-top. Using generated model templates, automatically extracted models or fine tuned models.

  1. AMS Simulation Environment
  2. AMS Designer
  3. Self-checking testbenches
  4. AMS Simulations (NCSim, irun, VCS-AMS)
  5. Pre-run circuits calibrations
  6. Behavioral Models (Verilog-A/MS, VHDL-AMS)
  7. Real Number Modeling
  8. Connect Modules
  9. eRM / UVM / OVM
  10. PSL assertions
  11. SV assertions
  12. Design Checks

Circuits Modeling / HDL / HVL

The most accurate or fast simulating models needed for the most demanding simulations. All HDL/HVL covered. Unique automatic model extraction available using SIMECT.

  1. Verilog
  2. VHDL
  3. Verilog-A
  4. Verilog-AMS
  6. SystemC
  7. SystemC-AMS
  8. SystemVerilog
  9. Automatic Model Extraction (SIMECT)

Static Electrical Rule Checking

Verification without simulation. Very fast static techniques to ensure your designs are reliable and bug-free.

  1. Floating devices, floating nets, floating pins
  2. Power domains continuity
  3. Unconnected inputs or shorted outputs
  4. Transistor gates connected directly to pads
  5. Maximum allowed series pass resistance
  6. Geometrical topological rules
  7. Antenna rules
  8. Forward bias diode check
  9. Mitigation of the electrostatic discharge (ESD) damage
  10. Mitigation of latch-up
  11. Fanout

Dynamic Electrical Rule Checking

Easily added on top of your simulations. Specific and accurate diagnostics to ensure your designs are reliable and bug-free.

  1. Dynamic Floating Nets
  2. High Impedance Nets
  3. DC Leakage Current Paths
  4. Excessive Element Current
  5. Current Leakage Mitigation
  6. Circuit Element Voltage
  7. Overstress Checks
  8. Reliability & SOA
  9. Noisy Nets
  10. Setup and Hold
  11. Dynamic Drive Capability

Physical Verification

Ensuring a smooth sign-off of the whole project. Technology accurate and closing the verification gaps.

  1. DRC
  2. LVS
  3. ERC post-layout
  4. Parasitic Extraction
  5. Post-layout Simulation
  6. ESD network
  7. Electromigration
  8. IR-drop
  9. Coupling

Interested in this Service?

“Project co-financed by the European Fund for Regional Development trough Competitiveness Operational Program 2014-2020”; and specifically for promotional materials, press releases, publications and web pages, the following text shall be added:
“The content of this material is not mandatory to represent the official position of the European Union or of the Romanian Government”.